The Apogee MiniDAC is a wonderful converter. But how does it work? Well, first of all, you can’t download the schematics from the net. So how it exactly works I don’t know. But looking at the components inside reveals at least some info.
Therefor my guess is as follows:
1. Two times CS8416 input digital receiver/PLL chip. Looking at the number of inputs and print layout, I guess the two units are needed because of the number of inputs to be switched.
2. Wavefront AL1402, that’s an ADAT receiver chip which decodes the 8 channel (optical) ADAT stream into 4 stereo pairs.
3. Xilink Spartan XC2S50 FPGA chip. 1728 logic cells, 32k RAM. Used for the interpolation and digital filter I guess. And also part of the dual clock concept.
4. Crystal running at 24,576 MHz. Must be a VCXO, since most dual clock/PLL implementations use a VCXO. This means first clock is generated by the CS8416’s PLL. This one suppresses high frequency jitter (lets say >10kHz). Second clock/PLL is build using the FPGA and VCXO. This has a narrow lock range, typically +/- 150 ppm, but good low frequency jitter suppression.
5. Analog Devices AD1955 DAC chip. That’s a stereo DAC with current outputs and on chip analog volume control. I don’t think the volume control is used but I’m not sure.
6. Multiple types of Op-Amps, including OP275 (dual op-amp from Analog Devices) and OPA134UA (single op-amp from Texas Instruments).
So no Asynchronous Sample Rate Converter (ASRC) chips?
Well not on the MiniDAC itself but on the USB and Firewire board. More precisely, the AD1896 is used on the USB board and the SRC4190 on the Firewire board. These ASRC’s are required since in the USB and Firewire interfaces, the input channel (i.e. towards the computer) carries the active SPDIF/AES source. So for example the Firewire interface is set to 96kHz sample rate and the SPDIF input is selected and plays on 44.1 kHz. Then the Firewire input on the computer carries the digital stream coming from the 44.1kHz SPDIF source, but now sample rate converted by the ASRC to 96kHz. This enables recording of SPDIF/AES streams and is intended to be used with Analog to Digital converters without computer interface such as the Apogee MiniME.
Talking about the Firewire interface, it’s a BridgeCo design using their DM1100E chip. They have a nice paper on it called System design for audio record and playback with a computer using FireWire. It’s sort of an alternative to TC Electronic’s DICE chip, which is used in the famous Weiss converters. An interesting paper by TC Electronic on JetPLL and the DICE chip is called Clean Clocks, Once and for All? Both designs are based around an ARM processor. Note that the BridgeCo design didn’t survive and the DICE won … however ARM rules them all …